1. Field of the Invention
The present invention relates generally to methods for forming vias through dielectric layers within microelectronics fabrications. More particularly, the present invention relates to methods for forming vias of reproducible cross-sectional profile through dielectric layers within microelectronics fabrications.
2. Description of the Related Art
Common in the art of microelectronics fabrication is the use of silicon oxide layers formed through use of chemical vapor deposition (CVD) methods, such as thermal chemical vapor deposition (CVD) methods and plasma enhanced chemical vapor deposition (PECVD) methods employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material, for forming dielectric layers within microelectronics fabrications. Such dielectric layers may include, but not limited to, pre-metal dielectric (PMD) layers, inter-metal dielectric (IMD) layers and post metal dielectric (ie: passivation dielectric) layers. Silicon oxide dielectric layers formed within microelectronics fabrications through use of thermal chemical vapor deposition (CVD) methods and plasma enhanced chemical vapor deposition (PECVD) methods employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material are desirable within microelectronics fabrications since such silicon oxide dielectric layers are often formed with enhanced properties in comparison with silicon oxide dielectric layers formed through use of other methods and materials.
When employing, in particular, within advanced microelectronics fabrications silicon oxide dielectric layers formed at least in part through use of plasma enhanced chemical vapor deposition (PECVD) methods employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material as dielectric layers through which are desired to form comparatively high areal density narrow linewidth vias to underlying structures, such as but not limited to underlying patterned conductor layer structures, it is common in the art of advanced microelectronics fabrication to form through such silicon oxide dielectric layers at least one wine glass shaped via, as illustrated in FIG. 1.
Shown in FIG. 1 is a substrate layer 10 having formed thereupon a series of patterned silicon oxide dielectric layers 12a, 12b and 12c at least the top surfaces of which are formed through use of a plasma enhanced chemical vapor deposition (PECVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material, where the series of patterned silicon oxide dielectric layers 12a, 12b and 12c defines a pair of wine glass shaped vias 16a and 16b. Formed upon the series of patterned silicon oxide dielectric layers 12a, 12b and 12c is a corresponding series of patterned photoresist layers 14a, 14b and 14c which assist in defining the location of the pair of wine glass shaped vias 16a and 16b. As is understood by a person skilled in the art, the wine glass shape of each of the wine glass shaped vias 16a and 16b is desirable to assure optimal step coverage when subsequently filling within the pair of wine glass shaped vias 16a and 16b a blanket conductor layer when further fabricating the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1.
In order to form the wine glass shaped profile within each of the wine glass shaped vias 16a or 16b within the pair of wine glass shaped vias 16a and 16b, there is typically employed when forming the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1 from a corresponding microelectronics fabrication employing a blanket silicon oxide dielectric layer formed beneath the patterned photoresist layers 14a, 14b and 14c either: (1) a sequential partial anisotropic etch/partial isotropic etch/complete anisotropic etch method for forming the patterned silicon oxide dielectric layers 12a, 12b and 12c from the blanket silicon oxide dielectric layer; or (2) a sequential partial isotropic etch/complete anisotropic etch method for forming the patterned silicon oxide dielectric layers 12a, 12b and 12c from the blanket silicon oxide dielectric layer. The anisotropic etch methods employed within the foregoing sequential etch methods are typically, but not exclusively, reactive ion etch (RIE) anisotropic etch methods, while the isotropic etch methods employed within the foregoing sequential etch methods are typically, although not exclusively, wet chemical etch methods.
While a microelectronics fabrication having formed therein a series of patterned silicon oxide dielectric layers, such as the series of patterned silicon oxide dielectric layers 12a, 12b and 12c as illustrated in FIG. 1, which define a pair of wine glass shaped vias, such as the pair of wine glass shaped vias 16a and 16b as illustrated within FIG. 1, is desirable within the art of microelectronics fabrication, such microelectronics fabrications are not formed entirely without problems within microelectronics fabrication. In particular, it is common in the art of microelectronics fabrication for a series of patterned photoresist layers, such as the series of patterned photoresist layers 14a, 14b and 14c as illustrated in FIG. 1, to at least partially delaminate from the surfaces of a series of patterned silicon oxide dielectric layers, such as the series of patterned silicon oxide dielectric layers 12a, 12b and 12c as illustrated in FIG. 1, thus forming a microelectronics fabrication whose schematic cross-sectional diagram is similar to the schematic cross-sectional diagram as illustrated in FIG. 2.
Shown in FIG. 2 is a schematic cross-sectional diagram of a microelectronics fabrication largely equivalent to the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1, but wherein: (1) each patterned photoresist layer 14a, 14b or 14c within the series of patterned photoresist layers 14a, 14b and 14c as illustrated in FIG. 1 is partially delaminated in forming the series of partially delaminated patterned photoresist layers 14a', 14b' and 14c'; (2) the corresponding series of patterned silicon oxide dielectric layers 12a, 12b and 12c is thus over-etched in forming the series of over-etched patterned silicon oxide dielectric layers 12a', 12b' and 12c'; and (3) the pair of wine glass shaped vias 16a and 16b is over-etched in forming the pair of over-etched wine glass shaped vias 16a' and 16b'.
Microelectronics fabrications whose schematic cross-sectional diagrams correspond with the microelectronics fabrication as illustrated in FIG. 2 are undesirable within advanced microelectronics fabrication since it is often difficult to form fully functional or reliable conductor contact or interconnection layers within over-etched wine glass shaped vias, such as the over-etched wine glass shaped vias 16a' and 16b' as illustrated in FIG. 2. It is thus desirable in the art of microelectronics fabrication to provide methods and materials through which wine glass shaped vias may be formed through silicon oxide dielectric layers formed through use of chemical vapor deposition (CVD) methods employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material, such as plasma enhanced chemical vapor deposition (PECVD) methods employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material, without over-etching those wine-glass shaped vias due to partial delamination of patterned photoresist layers which are employed in defining the location of those wine glass shaped vias, that the present invention is generally directed.
Various methods have been disclosed in the art of microelectronics fabrication, and in particular within the art of integrated circuit microelectronics fabrication, for forming wine glass shaped vias and wine glass shaped structures within microelectronics fabrications.
For example, Liu et al., in U.S. Pat. No. 5,180,689, discloses a method for forming within an integrated circuit microelectronics fabrication a wine glass shaped via through a multilayer dielectric layer within the integrated circuit microelectronics fabrication. The method employs a sequential partial anisotropic etch/partial isotropic etch/complete anisotropic etch method, along with a single patterned photoresist layer formed upon the multilayer dielectric layer, when forming the wine glass shaped via through the multilayer dielectric layer. The wine glass shaped via so formed is formed while avoiding a high temperature reflow of the resulting patterned multilayer dielectric layer.
In addition, Meng et al, in U.S. Pat. No. 5,453,403, discloses a similar method for forming within an integrated circuit microelectronics fabrication a wine glass shaped via through a dielectric layer within the integrated circuit microelectronics fabrication. The method employs a sequential partial anisotropic etch/partial isotropic etch method for forming a bowl shaped via partially through the dielectric layer while employing a single patterned photoresist layer as an etch mask layer in defining the location of the bowl shaped via. The patterned photoresist layer is then removed and the bowl shaped via is etched through use of an argon sputtering plasma anisotropic etch method to form a wine glass shaped via completely through the dielectric layer while simultaneously planarizing and smoothing sharp edges of the dielectric layer.
Further, Hsu, in U.S. Pat. No. 5,552,343, discloses a method for forming within an integrated circuit microelectronics fabrication a wine glass shaped via through a boron and phosphorus doped silicon oxide dielectric layer formed employing a tetra-ethyl-ortho-silicate (TEOS) silicon source material within the integrated circuit microelectronics fabrication. The method employs a buffered oxide etchant (BOE) to remove a densified layer of the boron and phosphorus doped silicon oxide dielectric layer prior to forming thereupon a patterned photoresist layer which is employed in defining the location of the wine glass shaped via. Through the method, there is formed the wine glass shaped via with a small entry angle at the surface of the boron and phosphorus doped silicon oxide dielectric layer.
Finally, Kim, in U.S. Pat. No. 5,622,883 discloses a method for forming within an integrated circuit microelectronics fabrication both a wine glass shaped via through a dielectric layer and a wine glass shaped landing pad contacting a wine glass shaped conductive contact stud layer formed within the wine glass shaped via. The method employs a sequential partial isotropic etch/complete anisotropic etch method for forming the wine glass shaped via through the dielectric layer.
Desirable within the art of microelectronics fabrication are additional methods and materials through which a wine glass shaped via may be formed through a silicon oxide dielectric layer formed through use of a chemical vapor deposition (CVD) method, such as a plasma enhanced chemical vapor deposition (PECVD) method, employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material, within a microelectronics fabrication without over-etching the wine-glass shaped vias due to partial delamination from the silicon oxide dielectric layer of a patterned photoresist layer employed in defining the location of the wine glass shaped via. More particularly desirable within the art of integrated circuit microelectronics fabrication are methods and materials through which a wine glass shaped via may be formed through a silicon oxide dielectric layer formed through use of a chemical vapor deposition (CVD) method, such as a plasma enhanced chemical vapor deposition (PECVD) method, employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material, within an integrated circuit microelectronics fabrication without over-etching the wine-glass shaped via due to partial delamination from the silicon oxide dielectric layer of a patterned photoresist layer employed in defining the location of the wine glass shaped via. It is towards the foregoing goals that the present invention is more specifically directed.